30+ years of experience in architecture, implementation and optimization of software, hardware, thermal, optical and mechanical systems. 34 U.S. patents issued. B. Sc. Physics (with honors), Clarkson, 1980.
TFI / xVI: Lead researcher on high-efficiency / low-cost TLC system
2014-current Designed large-area 130 W/cm2 micro-channel cooler for TPV tiles
Designed small 1500 W/cm2 semi-passive cooler for aerospace applications
Designed eye-safe system for powering drone at ~10 km via laser/telescope
SpaceWatts: Led design and prototyping of dense-receiver-array CPV for 1000x
2007-2014 concentration using low-cost mirrors made with flat glass. Design had high
efficiency, few parts/Watt & potential for lower LCOE than Fresnel HCPV.
DreamWafer: Led architecture of hardware/software integration accelerator featuring
2006-2013 rapid prototyping and any-connection debug for high-end circuit boards
Lead industrial technologist on 7-university project for largest-known
(250 cm2) ASIC, with >1 million I/Os for alignment insensitive contacts.
PROMPT: 12 years on Board of PROMPT (Gov’t/University/Industry funding organization),
2002-2021 also chaired PROMPT’s project evaluation committees for 12 years.
Hyperchip Architected and optimized extreme-performance router data planes for
2005-2015 Altera, Xilinx and Achronix FPGAs and leading-edge memories.
(CTO) Designed key algorithms for FPGA data planes to achieve 4x ASIC density.
* Ultra-efficient latency-tolerant queue management for DRAM queues
* Created pipeline architecture for simple single-cycle pipelining in FPGAs
* Created Longest-Prefix-Match CAM with ~40x the density of TCAM
Architected FPGA-based PCI-e-card terabit router accelerators.
Hyperchip: Raised over $100M, built engineering team to over 200 people,
1997-2004 recruited experienced management, and then returned to technical work.
(President Led design of first scalable traffic management for packet networks, which
and CTO) tier-1 carriers stated delivered the world’s best QoS for packet networks.
Pioneered massively parallel semiconductors for network equipment with
first-pass success on the largest ASIC IBM had ever made for a 3rd party.
Designed the first scalable routing protocols and route-table manager.
* Developed logic to reduce 768-bit ECC implementation in FPGA by 16x.
* Developed algorithms to shrink 160 Gb/s FPGA packet switch 10x.
* Developed single-cycle-update BCAMs 70x smaller than standard version.
VCS: Lead architect on Vermont Views 4.0, HighTest 2.0, and Ghost 1.5.
1991-1996 Created world’s fastest ‘life’ cellular algorithm (10X faster than previous record).
IBM: Won the IBM General Technology Division’s highest award for innovation
1980-1988 for developing a software environment with over 100 highly-configurable ‘apps’
including the first full-screen e-mail and file managers for IBM computers.
Customizable context-sensitive commands + longest-prefix-match intelligent
interpretation won the software the highest ratings for usefulness, friendliness
and flexibility of all software used in IBM Burlington.